For specific problem areas, we have developed a range of fixed-duration consulting packages, usually lasting two to five days. These typically involve training and focused problem solving in the specific client chip project in progress at the time. The currently available packages are:
- Verification Planning. This comes in two forms. In the first, Verilab will perform the entire planning process. This is appropriate where Verilab also has expertise in the specific application domains involved. Or, where the domain expertise reside primarily with the client, Verilab will provide a smaller, sometimes one-person, planning team to coordinate the planning effort, mentoring the client engineers to reach the levels of planning quality our experience shows are necessary for success.
- Verification Capability Auditing. This package involves a detailed audit of your overall verification capability, apart from any specific project.
- "Chip RescueSM". In this package, Verilab consultants act as "smoke jumpers" to provide the best possible chance of rescuing a stressed project. Our rescue-trained consultants are used to working in high stress situations, and are expert in applying the broadest range of technologies and methods to get the job finished safely.
- Clock Domain Crossing (CDC) Workshop. A comprehensive training and consultancy package targeting the verification and design of CDC logic. The training material examines the fundamental causes of CDC issues, provides a detailed analysis of synchronizer circuits and presents a pragmatic Assertion-Based Verification methodology using SystemVerilog Assertions in a tool independent manner. The workshop includes consultancy-based analysis and interactive peer reviews of the customer's synchronization logic and proposes appropriate solutions to enhance design and verification effectiveness.