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Archive for January, 2009

Verilab OCP article picked up by EDA Designline

Tuesday, January 13th, 2009 by Jason Sprott

Mark Litterick’s “Architecting the OCP uVC verification component” article written about in a previous blog has also been picked up by EDA Designline

Litterick’s OCP-IP newsletter article uses Verilab’s OCP uVC VIP as an example

Wednesday, January 7th, 2009 by Jason Sprott

Mark Litterick’s OCP-IP December 2008 newsletter article demonstrates how two key aspects of OCP – profiles and transactions — were adopted as fundamental building blocks for the architecture of a verification component targeted at constrained-random validation of OCP components and systems.

The article uses the Verilab OCP uVC as an example. This uVC is a mixed-language OCP compliant verification component that supports a major subset of Open Core Protocol Specification 2.2. The OCP uVC is implemented using SystemVerilog and e verification languages and complies with both the Open Verification Methodology (OVM) and e Reuse Methodology (eRM). The verification component can be used in SystemVerilog only applications without the Specman layer (or license), or it can be used in Specman-based verification environments as a regular eVC.

The OCP-IP article can be downloaded here

The full whitepaper can be downloaded here

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