Here’s a new English term I’ve just coined: reuseless code. It refers to code that was written in such a reusable way that it can’t be used in any way. Writing reusable code is a noble cause, but before you start it is better to clarify where, why and how you think your code will ever be reused, if at all. Skip this step and you can be sure that, despite your good intentions, someone else will have to rewrite the whole thing later on. You can also be sure that your code will be unnecessarily and overwhelmingly complex.

In a testbench different parts are likely to be reused in different ways. Standard interfaces are the number one candidates for reuse in the pure sense of the term; it is quite probable that they will be plugged in as is into an altogether different project later on. Data generators (i.e. an Ethernet packet generator), base class libraries and generic packages (register package) follow close. In fact, if you’re lucky enough, you will probably be reusing someone else’s code yourself.
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Those of you who are members of the SystemVerilog User Group (SVUG) may have received an email describing several upcoming events.  For those of you not on the SVUG mailing list, here is the info:

SVUG has a simple goal to advance the SystemVerilog language and accelerate the adoption of associated tools, methods, IP, and training. If you are a design or verification professional looking for a fun, informative way to keep on top of the SystemVerilog ecosystem, then you absolutely should register for a fall user group meeting at one of following locations:

USA	Europe
Boston, MA October 15th Cafe Escadrille	Cambridge, UK October 9th Homerton College
Austin, TX October 17th Cool River Cafe	Munich, DE October 11th Sofitel Munich Bayerpost
San Jose October 18th Maggiano’s

These great locations will stimulate your SystemVerilog intellect with instructive tutorials and informative presentations, wonderful food & drink and best of all - the chance to mingle with your peers and the industries’ top SystemVerilog experts.

Click here to view each location’s agenda and schedule.

Verilab’s very own Jason Sprott and Mark Litterick will be presenting at a couple of the events.  Jason is presenting in Cambridge.  Mark is presenting in Munich.  If you’ve got a bit of spare time and are looking to learn more about SystemVerilog and meet up with other SV users, this is your chance!