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0-IN for CDC Verification Still Looks Pretty Good

Over 50% of chip designs today have >20 clock domains. This makes CDC verification pretty high up on the priority list. At Verilab we have our own CDC workshop, which is split into a design portion (it’s better to get CDC design right in the first place), and a verification portion, which focuses on using SystemVerilog Assertions and dynamic simulation. This gets our clients hitting the ground running with CDC really quickly, using the tools they have at their disposal today. However, we’re always on the lookout for other cool CDC verification techniques. I got an update yesterday of 0-IN’s CDC verification capabilities and they still look pretty good.

0-IN uses a 3 step approach to CDC verification:

  • Structural analysis of the design: identifies clock domains; identifies CDC synchronizers in the design; highlights missing/incorrect synchronization; reports combinatorial and sequential reconvergent CDC signals
  • Automatic assertion and coverage generation: these monitors and can be used as runtime checkers and functional coverage collectors in normal dynamic simulation.
  • CDC reconvergence: 0-IN corrupts signal values various effects of metastability during RTL simulations. 0-IN handles both combinational and sequential reconvergence.

0-IN uses a combination of formal static and dynamic simulation to complete the CDC verification. It’s a pretty sound solution, and looks to have the scope to handle the wackiest of CDC synchronization techniques.

The Q2 2007 Mentor Verification Horizons newsletter has a couple of light, but mildly interesting, CDC related articles worth a look. The white paper “Five Steps to Quality CDC Verification”, by Ping Yeung (Mentor Graphics), is also worth reading to learn a bit more about some CDC design techniques and reconvergence.

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