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Mark Litterick

Mark Litterick

Senior Vice President
Email Mark Litterick 

Mark Litterick co-founded Verilab in 2000, along with Tommy Kelly and Jason Sprott.

Graduating in 1986 with a First in Electrical and Electronic Engineering from Strathclyde University in Glasgow, Mark then spent the next twelve years gaining extensive verification and design experience working for GEC Marconi and Motorola. It was during this time that his unusually deep instinct for verification became apparent when he demonstrated to the designer of a specialized graphics ASIC that it was well within spec. limits and therefore pefectly reasonable to test if a circle-drawing unit within the chip could "draw a circle of radius zero". Needless to say, a potentially dangerous bug was found and eliminated and Mark began to develop the depth, precision, and intensity of skill and engineering approach for which he has become known and respected. 

Towards the end of the 90's, Mark then took a break from terrorizing designers and spent a year traveling the world to pursue his other passion of mountaineering, an ongoing adventure that in addition to his native Europe, has taken him to the Antipodes, Himalayas, North and South America, and (see photo) Greenland. So far.

Returning to the fray in 1999, he spent a year beginning to build individual consulting experience onto his core technical skills, before introducing Tommy and Jason and founding Verilab with them in early 2000. 

As a founder and Senior VP, Mark is among the most sought-after experts on Verilab's elite international team. He combines not only a rare level of mastery in the field of front-end verification and design, he is also a superb technical lead, coach, and teacher and helps clients achieve their goals as much by enabling their own team as by the code and plans he produces.

As part of that work of teaching and enabling other engineers, Mark has authored many technical papers, several of which have won awards including: "Pragmatic Simulation-Based Verification of Clock Domain Crossing Signals and Jitter Using SystemVerilog Assertions" (best paper at DVCon 2006), "SVA Encapsulation in UVM - Enabling Phase and Configuration-Aware Assertions" (best paper at DVCon 2013) and "Lies, Damned Lies, and Coverage" (honourable mention at DVCon 2015).

Available Resources

  • DVCon 2006: Using SystemVerilog Assertions in Gate-Level Verification Environments
  • Mentor Solutions Expo 2005: Focusing Assertion Based Verification Effort for Best Results
  • DVCon 2006: Pragmatic Simulation-Based Verification of Clock Domain Crossing Signals and Jitter Using SystemVerilog Assertions
  • SNUG Europe 2005: Utilizing Vera Functional Coverage in the Verification of a Protocol Engine for the FlexRay(TM) Automotive Communication Sytem
  • DAC 2005: Using SystemVerilog Assertions for Functional Coverage
  • MTV 2004: Robust Vera Coding Techniques for Gate-Level and Tester-Compliant SoC Verification Environments
  • SNUG Europe 2004: Robust Vera Coding Techniques for Gate-Level and Tester-Compliant SoC Verification Environments
  • Mentor Designer's Forum 2002: FPGA-Centric Functional Verification
  • SVUG 2007: Assertion-Based Verification using SystemVerilog
  • Application Note 2006: FPGA Protoyping in Verification Flows
  • OCP-IP Article 2008 - OCP Profiles and Transactions
  • OCP uVC
  • Verification Horizons June 2010: Simulation-Based FlexRayTM Conformance Testing - an OVM Success Story
  • EDA Tech Forum 2010: Simulation-Based FlexRayTM Conformance Testing using OVM
  • User2User 2010: Simulation-Based FlexRayTM Conformance Testing - an OVM Success Story
  • CDN Live EMEA 2011: FlexRayTM Conformance Testing using OVM
  • SNUG Ottawa 2012: UVM Sequence Item Based Error Injection
  • DVCon 2013: OVM to UVM Migration - or There and Back Again, a Consultant's Tale
  • DVCon 2013: Pragmatic Verification Reuse in a Vertical World
  • DVCon 2013: SVA Encapsulation in UVM - enabling phase and configuration aware assertions
  • Verification Horizons Feb 2013: OVM to UVM Migration, or 'There and Back Again, a Consultant's Tale'
  • DVCon 2014: Advanced UVM Register Modeling - There's More Than One Way to Skin A Reg
  • DVCon Europe 2014: Advanced UVM Tutorial
  • DVCon 2015: Lies, Damned Lies, and Coverage
  • SNUG Austin 2015: Mastering Reactive Slaves in UVM
  • Verification Workshops
  • DVCon Europe 2015: Advanced UVM Tutorial - Taking Reuse To The Next Level
  • DVCon 2016: Full Flow Clock Domain Crossing - From Source to Si
  • SNUG Germany 2016: Mastering Reactive Slaves in UVM
  • SNUG Austin 2018: Use the Sequence, Luke - Guidelines to Reach the Full Potential of UVM Sequences
  • DVCon Europe 2018: UVM Audit Tutorial
  • DVCon Europe 2019: Be a Sequence Pro to Avoid Bad Con Sequences
  • To Infinity And Beyond - Streaming Data Sequences In UVM

Work For Verilab