Since joining Verilab in 2004, JL has developed a consulting practice in verification planning, methodology development, and project execution with a wide range of clients in Europe, Asia, the Middle East, and the US. JL has presented workshops on verification methodology and planning around the world. He also has implemented verification environments in all of the major e and SystemVerilog libraries (eRM, VMM, and OVM). In addition to his consulting activities, JL has contributed to the EDA industry as Verilab's representative on the Accellera Verification IP Technical Subcommittee.
JL is well known in the electronic design automation (EDA) industry as the author of "Cool Verification", a blog about hardware verification from a consultant's perspective. He has also worked extensively on the application of social media to the EDA industry as a means of fostering collaboration in the wider engineering community.Before joining Verilab JL was a verification engineer at ServerEngines, LLC where he helped develop verification infrastructure from the ground up using SystemC. Prior to joining ServerEngines, JL was a Senior Verification Engineer in the Network Communications Group at Intel Corporation, where he developed verification environments and methodologies using Specman Elite for 1G and 10G Ethernet controllers.
JL received his Bachelors in Electrical Engineering from Purdue University in West Lafayette, Indiana. In his spare time JL enjoys cycling, travel, and yoga.
- The Myth of SystemVerilog Interoperability
- SNUG 2009: Using the New Features in VMM 1.1 for Multi-Stream Scenarios
- DVCon 2010: Stimulating Scenarios in the OVM and VMM
- SNUG 2010: Integrating e Verification IP in a VMM Testbench
- DVCon 2012: A 30 Minute Project Makeover Using Continuous Integration