Mark Litterick

Mark Litterick Graduated with a BSc in Electrical and Electronic Engineering from Strathclyde University in Glasgow, Scotland, 1986. After 10 years extensive design and verification experience working for GEC Marconi and Motorola, Mark took a year out to travel the world and pursue his passion for mountaineering. More recently, Mark has just returned from a month-long expedition to Greenland (see photo) in which, among other climbs, he made seven first ascents.

With renewed enthusiasm, Mark returned to operate as freelance consultant in the UK before jointly founding Verilab in 2000. Mark continues to work for Verilab as senior verification consultant and is currently based in Munich, Germany.

Mark has authored several papers, including "Pragmatic Simulation-Based Verification of Clock Domain Crossing Signals and Jitter Using SystemVerilog Assertions", which was voted best paper at DVCon 2006.