- April 18, 2009
SNUG 2009 Multi-Stream Scenario Paper Now Available - April 16, 2009
Verilab OCP uVC added to OCP-IP Library - January 13, 2009
Verilab OCP article picked up by EDA Designline
Mark Litterick
Consultant
Mark Litterick Graduated with a BSc in Electrical and Electronic Engineering from Strathclyde University in Glasgow, Scotland, 1986. After 10 years extensive design and verification experience working for GEC Marconi and Motorola, Mark took a year out to travel the world and pursue his passion for mountaineering. More recently, Mark has just returned from a month-long expedition to Greenland (see photo) in which, among other climbs, he made seven first ascents.
With renewed enthusiasm, Mark returned to operate as freelance consultant in the UK before jointly founding Verilab in 2000. Mark continues to work for Verilab as senior verification consultant and is currently based in Munich, Germany.
Mark has authored several papers, including "Pragmatic Simulation-Based Verification of Clock Domain Crossing Signals and Jitter Using SystemVerilog Assertions", which was voted best paper at DVCon 2006.
Available Resources
- FPGA-Centric Functional Verification
- Robust Vera Coding Techniques for Gate-Level and Tester-Compliant SoC Verification Environments
- "Robust Vera Coding Techniques for Gate-Level and Tester-Compliant SoC Verification Environments (SNUG Europe 2004)
- Pragmatic Simulation-Based Verification of Clock Domain Crossing Signals and Jitter Using SystemVerilog Assertions
- Using SystemVerilog Assertions in Gate-Level Verification Environments
- Focusing Assertion Based Verification Effort for Best Results
- Using SystemVerilog Assertions for Functional Coverage
- Utilizing Vera Functional Coverage in the Verification of a Protocol Engine for the FlexRay(TM) Automotive Communication Sytem
- SVUG Europe 2007: Assertion-Based Verification using SystemVerilog
- Application Note: FPGA Protoyping in Verification Flows
- OCP-IP Article - OCP Profiles and Transactions
- OCP uVC
