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Kevin Johnston

Senior Staff Engineer
Email Kevin Johnston 

Kevin has over 35 years experience in the design and verification of digital ASIC's, processor cores and SoC's. Since joining Verilab in January of 2006, Kevin has assisted with the verification of a multi-threaded DSP core and taught a graduate course in processor architecture at the Universidade Federal do Rio Grande do Sul, Porto Alegre in Brazil. Prior to Verilab, Kevin worked at Motorola/Freescale designing and verifying 68K- and PowerPC-based SoC's, and at Texas Instruments as a design and test engineer.

Available Resources

  • White Paper 2008: Endian - From the Ground Up
  • SNUG Austin 2012 Best Paper: Taming Testbench Timing - Time's Up for Clocking Block Confusion
  • DVCon Europe 2015: Is Your Testing N-wise or Unwise?
  • SNUG Austin 2017: Verification Prowess with the UVM Harness
  • DVCon2018: Code examples for "My Testbench Used to Break, Now it Bends"
  • DVCon2018: My Testbench Used to Break! Now it Bends

Work For Verilab