JP Sharkey

JP Sharkey joined Verilab in October 2002. During his tenure at Verilab he has been active in several taped-out verification projects including a 10Gb MAC Ethernet Controller, a FlexRay Controller, a multi-stage pipeline extensions interface and recently, a combined CPU/Northbridge device. His ability to contribute successfully to projects is greatly assisted by over 20 years experience in software and hardware design plus strong skills in methodologies and programming languages such as the eRM, Specman e, Vera, SystemC, C++ and Java.

Prior to joining Verilab, JP was a Senior Design Engineer of PC Single Board Computers at Microbus Designs, involved in all aspects of design from schematic capture, PCB design, database maintenance, and test system development.

JP demands challenges, both mentally and physically. He enjoys technical reading and obtained MCSD and Java Certification in his spare time. Keen on sports, he has joined several local soccer teams since moving to the States in 2005.

JP holds a Bachelors of Science degree in Electrical and Electronic Engineering with Computing Science from Glasgow University, and MSc in System Level Integration from the Institute of System Level Integration (ISLI) in Livingston, Scotland.