JL Gray

JL Gray has been with Verilab, where he is currently serving as an Associate Principal, since 2004. Since then, JL has been traveling around the US and Europe (France and Germany) working with clients to develop advanced verification environments using Specman, SystemVerilog, SystemC, C++, and Vera. During his time at Verilab, JL has worked on a number of projects related to topics including AMBA/AHB, DDR3, FBDIMM, CAMBIST, and OCP. JL is also the author of Cool Verification, a blog about hardware verification from a consultant's perspective.

Before joining Verilab JL was a verification engineer at ServerEngines, LLC where he helped develop verification infrastructure from the ground up using SystemC.

Prior to joining ServerEngines, JL was a Senior Verification Engineer in the Network Communications Group at Intel Corporation, where he developed verification environments and methodologies using Specman Elite for 1G and 10G Ethernet controllers.

JL received his Bachelors in Electrical Engineering from Purdue University in West Lafayette, Indiana. In his spare time JL enjoys cycling, travel, and yoga.