Recent Press and Postings


Jeff Montesano

Jeff Montesano

Senior Consultant
Email Jeff Montesano 
High Resolution Image

Jeff has been with Verilab since 2011 and is a Senior Consultant specializing in constrained-random verification using SytemVerilog/UVM. He has authored several award winning papers over the years, including the DVCon USA best paper in 2018. Over the span of his 19-year career, he has worked throughout North America and Europe on projects ranging from networking equipment, to military, consumer, and automotive electronics.

Available Resources

  • SNUG Ottawa 2012: UVM Sequence Item Based Error Injection
  • DVCon 2014: Verification Mind Games - how to think like a verifier
  • SNUG Austin 2015: Mastering Reactive Slaves in UVM
  • SNUG Germany 2016: Mastering Reactive Slaves in UVM
  • SNUG Austin 2016: Configuring a Date with a Model
  • SNUG Austin 2016: Configuring a Date with a Model - A Guide to Configuration Objects and Register Models
  • SNUG Austin 2017: Verification Prowess with the UVM Harness
  • DVCon2018: Code examples for "My Testbench Used to Break, Now it Bends"
  • DVCon2018: My Testbench Used to Break! Now it Bends
  • SNUG Austin 2018: Use the Sequence, Luke - Guidelines to Reach the Full Potential of UVM Sequences
  • DVCon US 2019 WorkShop: Be a Sequence Pro

Work For Verilab